## Generated SDC file "SampleDBoard.sdc"

## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"

## DATE    "Tue Sep 15 11:49:24 2020"

##
## DEVICE  "EP4CE115F29C8"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {IOclk0} -period 20.000 -waveform { 0.000 10.000 } [get_ports {IOclk0}]
create_clock -name {DclkB} -period 3.333 -waveform { 0.000 1.666 } [get_ports {DclkB}]
create_clock -name {DclkA} -period 3.333 -waveform { 0.000 1.666 } [get_ports {DclkA}]


#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {UCLK|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {UCLK|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {IOclk0} [get_pins {UCLK|altpll_component|auto_generated|pll1|clk[1]}] 
create_generated_clock -name {UCLK|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {UCLK|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 5 -master_clock {IOclk0} [get_pins {UCLK|altpll_component|auto_generated|pll1|clk[2]}] 
create_generated_clock -name {UCLK|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {UCLK|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -master_clock {IOclk0} [get_pins {UCLK|altpll_component|auto_generated|pll1|clk[3]}] 
create_generated_clock -name {UCLK|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {UCLK|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 12 -divide_by 5 -master_clock {IOclk0} [get_pins {UCLK|altpll_component|auto_generated|pll1|clk[4]}] 
create_generated_clock -name {UBrd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]} -source [get_pins {UBrd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -phase -45.000 -master_clock {DclkB} [get_pins {UBrd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]}] 
create_generated_clock -name {UBrd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]} -source [get_pins {UBrd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 6 -phase -7.500 -master_clock {DclkB} [get_pins {UBrd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]}] 
create_generated_clock -name {UArd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]} -source [get_pins {UArd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -phase -45.000 -master_clock {DclkA} [get_pins {UArd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]}] 
create_generated_clock -name {UArd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]} -source [get_pins {UArd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 6 -phase -7.500 -master_clock {DclkA} [get_pins {UArd|URX|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]}] 


#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************



#**************************************************************
# Set Input Delay
#**************************************************************



#**************************************************************
# Set Output Delay
#**************************************************************



#**************************************************************
# Set Clock Groups
#**************************************************************



#**************************************************************
# Set False Path
#**************************************************************



#**************************************************************
# Set Multicycle Path
#**************************************************************



#**************************************************************
# Set Maximum Delay
#**************************************************************



#**************************************************************
# Set Minimum Delay
#**************************************************************



#**************************************************************
# Set Input Transition
#**************************************************************

